- 软件介绍
- 相关文章
The AD9517-3* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz may be used.
The AD9517-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
The AD9517-3 features four LVPECL outputs (in two pairs); four LVDS outputs (in two pairs); and eight CMOS outputs (two per LVDS output). The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
The AD9517-3 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V.
The AD9517-3 is specified for operation over the standard industrial range of 40C to +85C.
*AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-3 is used, it is referring to that specific member of the AD9517 family.
